module ARCH_4B_Q (FUNCTIONS, CHANNELS, QUEUE, VARIABLE_ARRAY, MESI_CACHE, VIRTUAL) is

-------------------------------------------------------------------------------
-- Architecture of systems communicating by means of 2*N shared variables and a
-- queue. The shared variables are represented as the cells a[0], ..., a[N-1]
-- and c[0], ..., c[N-1] of two N-variable arrays. The queue is represented by 
-- a shared variable with operations fetch_and_store and compare_and_swap.
-------------------------------------------------------------------------------

process Arch_4b_q [NCS: Pid, CS: Access, A, B, C: Operation, MU: Latency] is
   par NCS, CS, A, B, C in
      Protocol [NCS, CS, A, B, C]
    ||
      L [NCS, CS, A, B, C, MU]
   end par
end process

-------------------------------------------------------------------------------
-- Auxiliary process for compositional generation: protocol without latencies
-------------------------------------------------------------------------------

process Protocol [NCS: Pid, CS: Access, A, B, C: Operation] is
   par A, B, C in
      par
         P [NCS, CS, A, B, C] (0 of Pid)
       ||
         P [NCS, CS, A, B, C] (1 of Pid)
       ||
         P [NCS, CS, A, B, C] (2 of Pid)
       ||
         P [NCS, CS, A, B, C] (3 of Pid)
       ||
         P [NCS, CS, A, B, C] (4 of Pid)
      end par
    ||
      par
         Variable_Array [A] (N)
       ||
         Variable_Array [C] (0 of Nat)
       ||
         Queue [B] (N)
      end par
   end par
end process

-------------------------------------------------------------------------------
-- Auxiliary process for inserting latencies
-------------------------------------------------------------------------------

process L [NCS: Pid, CS: Access, A, B, C: Operation, MU: Latency] is
   var
      a, c: Cache_Array,
      a_i, b, c_i: Cache,
      index, pid: Pid,
      acc: Access,
      op: Operation,
      cop: Cached_Operation
   in
      a := cache_array (cache (Invalid));
      b  := cache (Invalid);
      c := cache_array (cache (Invalid));
      loop
         alt
            A (?op, ?index, ?any Nat, ?pid);
            a_i := a[Nat (index)];
            cop := update_caches (pid, op, !?a_i);
            a[Nat (index)] := a_i;
            MU (cop, pid)
          []
            B (?op, ?any Nat, ?any Nat, ?pid);
            cop := update_caches (pid, op, !?b);
            MU (cop, pid)
          []
            B (?op, ?any Nat, ?any Nat, ?any Bool, ?pid);
            cop := update_caches (pid, op, !?b);
            MU (cop, pid)
          []
            C (?op, ?index, ?any Nat, ?pid);
            c_i := c[Nat (index)];
            cop := update_caches (pid, op, !?c_i);
            c[Nat (index)] := c_i;
            MU (cop, pid)
          []
            CS (?acc, ?pid);
            if acc == Enter then
               MU (acc, pid)
            end if
          []
            NCS (?pid);
            MU (Work, pid)
         end alt
      end loop
   end var
end process

end module